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In [[digital electronics]], an '''Address decoder''' is a [[decoder]] circuit that has two or more bits of an [[address bus]] as inputs and that has one or more device selection lines as outputs.<ref name="TAoE">{{cite book|author=[[Paul Horowitz]] and [[Winfield Hill]]|title=[[The Art of Electronics]]|edition=Second edition|year=1989|publisher=Cambridge University Press|isbn=9780521370950|page=685,766}}</ref> When the address for a particular device appears on the address bus, the address decoder asserts the selection line for that device. A separate single-device address decoder may be incorporated into each device on an address bus, or a single address decoder may serve multiple devices.<ref>{{cite book
|author=S. J. Cahill |title=Digital and microprocessor engineering |url=http://books.google.com/books?id=zwJTAAAAMAAJ |edition=Second edition |year=1993 |publisher=Ellis Horwood |isbn=9780132133982 |page=489-494 }}</ref> In the latter case, an address decoder with N address input bits can serve up to 2<sup>N</sup> separate devices. Several members of the [[List of 7400 series integrated circuits|7400 series]] of [[integrated circuit]] are address decoders. An example is the 74154 . This address decoder has four address inputs and sixteen (i.e., 2<sup>4</sup> ) device selector outputs. An address decoder is also referred to as a "[[demultiplexer]]" or "demux," although these terms are more general and can refer to devices other than address decoders. The 74154 mentioned above can be called a "4-to-16 demux." Address decoders are fundamental building blocks for systems that use buses. They are represented in all integrated circuit families and processes and in all standard [[FPGA]] and [[ASIC]] libraries. They are discussed in introductory textbooks in digital logic design.<ref name="TAoE"/>
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