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[[Image:Superscalarpipeline.svg|thumb|300px|A five-stage pipelined [[superscalar]] [[Microprocessor|processor]], capable of issuing two instructions per cycle. It can have two instructions in each stage of the pipeline, for a total of up to 10 instructions (shown in green) being simultaneously executed.]]
In addition to instruction-level parallelism from pipelining, some processors can issue more than one instruction at a time. These are known as [[superscalar]] processors. Instructions can be grouped together only if there is no [[data dependency]] between them. [[Scoreboarding]] and the [[Tomasulo algorithm]] (which is similar to scoreboarding but makes use of [[register renaming]]) are two of the most common techniques for implementing out-of-order execution and instruction-level parallelism .
===Data parallelism===
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