Address decoder: Difference between revisions

Revision as of 22:47, 19 September 2010

Revision as of 04:30, 4 October 2010

Line 1:

[[Image:2to4demux.pngsvg|thumb|right|The four states of a 2-to-4 Decoder]]

In [[digital electronics]], an '''address decoder''' is a [[decoder]] circuit that has two or more bits of an [[address bus]] as inputs and that has one or more device selection lines as outputs.<ref name="TAoE">{{cite book|author=[[Paul Horowitz]] and [[Winfield Hill]]|title=[[The Art of Electronics]]|edition=2nd|year=1989|publisher=Cambridge University Press|isbn=9780521370950|page=685,766}}</ref> When the address for a particular device appears on the address bus, the address decoder asserts the selection line for that device. A separate single-device address decoder may be incorporated into each device on an address bus, or a single address decoder may serve multiple devices.<ref>{{cite book

|author=S. J. Cahill