Address decoder: Difference between revisions

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[[Image:2to4demux.svg|thumb|right|The four states of a 2-to-4 Decoder]]

In [[digital electronics]], an '''address decoder''' is a [[decoder]] circuit that has two or more bits of an [[address bus]] as inputs and that has one or more device selection lines as outputs.<ref name="TAoE">{{cite book|author=[[Paul Horowitz]] and [[Winfield Hill]]|title=[[The Art of Electronics]]|edition=2nd|year=1989|publisher=Cambridge University Press|isbn=9780521370950978-0-521-37095-0|page=685,766}}</ref> When the address for a particular device appears on the address bus, the address decoder asserts the selection line for that device. A separate single-device address decoder may be incorporated into each device on an address bus, or a single address decoder may serve multiple devices.<ref>{{cite book

|author=S. J. Cahill

|title=Digital and microprocessor engineering

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|year=1993

|publisher=Ellis Horwood

|isbn=9780132133982978-0-13-213398-2

|pages=489–494

}}</ref> When a single address decoder serves multiple devices, an address decoder with n address input bits can serve up to 2ⁿ separate devices. Several members of the [[List of 7400 series integrated circuits|7400 series]] of [[integrated circuit]] are address decoders. An example is the 74154.<ref>[http://web.mit.edu/6.115/www/datasheets/74hc154.pdf Datasheet for 74HC154]</ref>