Memory hierarchy: Difference between revisions

Revision as of 23:49, 9 February 2006

Revision as of 18:49, 12 February 2006

Line 5:

The memory hierarchy in most computers is as follows:

* [[Processor register]]s – fastest possible access,ususally in 1 CPU cycle. But only hundreds of bytes

* Level 1 (L1) [[CPU cache|cache]] – often accessed in just a few cycles, usually tens of kilobytes

* Level 2 (L2) [[CPU cache|cache]] – higher latency than L1 by 2× to 10×, often 512KB or more

* Level 3 (L3) [[CPU cache|cache]] – (optional) higher latency than L2, often multiple MB's

* [[Primary storage|Main memory]] ([[DRAM]]) – may take hundreds of cycles, but can be multiple gigabytes.

* [[Disk storage]] – hundreds of thousands of cycles latency, but very large

==Management ==

Modern [[programing lanaguage]]s are mainly assuming two levels of memory: main memory and disk storage, tough directly accessing registers are allowable in rare cases. Programmers are responsible for moving data between disk and memory through file I/O. Hardware is in charge of moving data between memory and caches. Compilers are trying to optimize the usage of caches and registers.

==See also==

* [[Virtual memory]]