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== Overview ==
NISC is a statically-scheduled horizontal nanocoded architecture (SSHNA). The term "statically scheduled" means that the operation scheduling and hazard handling are done by a compiler. The term "horizontal nanocoded" means that NISC does not have any predefined [[instruction set]] or [[microcode]]. The compiler generates nanocodes which directly control functional units, registers and multiplexers of a given datapath. Giving low-level control to the compiler enables better utilization of datapath resources, which ultimately result in better performance. The benefits of NISC technology are:
# Simpler controller: no hardware scheduler, no instruction decoder
# Better performance: more flexible architecture, better resource utilization
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