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<ref>http://commons.wikimedia.org/wiki/File:Basic_JFET.png</ref>
<ref>http://commons.wikimedia.org/wiki/File:Actual_JFET.png</ref>
FET terminals are:
# SOURCE (S) : through which the majority carriers enter the channel.
Conventional current entering the channel at S is designated by IS.
# DRAIN (D) : through which the majority carriers leave the channel.
Conventional current entering the channel at D is designated by ID.
Drain to Source voltage is VDS.
# GATE (G) : is the common terminal for the other two regions surrounding the channel.
By applying voltage to G, we can control ID.
Conventional current entering the channel at G is designated by IG.
<ref name=Prathamesh>
{{cite book
|author=Millman
|title=Electronic devices and circuits
|year=1985
|pages=384–385
|publisher=McGraw-Hill international book company
|___location=Singapore
|isbn=0-07-Y85505-6}}
</ref>
== Terminals ==
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