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* [[Fault tolerant]], [[distributed architecture]]
* Modular, layered [[microkernel]] architecture
* [[Event-driven architecture|Event-driven]], deterministic real-time response
* Asynchronous direct [[message-passing]] model
* Scalable hybrid [[Multi-core processor|multicore]] solution exploiting the advantages from both SMP and AMP models
* [[memory protection|Memory protected]]
* Centralized [[error handling]] and remediation