Revision as of 15:30, 9 May 2012 edit Helpful Pixie Bot (talk \| contribs) Bots 571,497 edits m ISBNs (Build KE) ← Previous edit		Revision as of 23:30, 6 August 2012 edit undo ChrisGualtieri (talk \| contribs) Pending changes reviewers, Rollbackers 457,369 edits m Typo fixing, typos fixed: etc) → etc.), eg → e.g. using AWB Next edit →
Line 20: The architecture encodes instructions compactly, using 16 bits for frequently used instructions (with up to three operands) and 32 bits for less frequently used instructions (with up to 6 operands). Almost all instructions execute in a single cycle, and the architecture is event-driven in order to decouple the timings that a program needs to make from the execution speed of the program. A program will normally perform its computations and then wait for an [[Event (computing)\|event]] (ege.g. a [[Message passing\|message]], time, or external I/O event) before continuing. Processors with this architecture include the [[XCore XS1-G4]] and [[XCore XS1-L1]]. Line 112: == External links == * [https://www.xmos.com/ XMOS website] (Free registration required to access documents etc.) {{RISC-based processor architectures}}

XCore Architecture: Difference between revisions