Signoff (electronic design automation): Difference between revisions

Revision as of 16:08, 6 June 2012

Revision as of 22:17, 28 August 2012

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Signoff checks have become more complex as [[VLSI]] designs approach [[32nm]] and [[22nm]] process nodes because of the increased impact of previously ignored (or more crudely approximated) second order effects. There are several categories of signoff checks.

* [[Design rule checking|DRC]] - Also sometimesanusha is mad known as geometric verification, this involves verifying if the design can be reliably [[semiconductor fabrication|manufactured]] given current photolithography limitations. In advanced process nodes, [[Design for manufacturability (IC)|DFM]] rules are upgraded from optional (for better yield) to required.

* [[Layout versus schematic|LVS]] - Also known as schematic verification, this is used to verify that the [[placement (electronic design automation)|placement]] and [[routing (electronic design automation)|routing]] of the [[standard cell]]s in the design has not altered the functionality of the constructed circuit.

* [[Formal verification]] - Here, the logical functionality of the post-[[Integrated circuit layout|layout]] netlist (including any layout-driven optimization) is verified against the pre-layout, post-[[logic synthesis|synthesis]] [[netlist]].