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The instruction set comprises both a (more or less standard) sequential programming model, and instructions that implement multi-threading, multi-core and I/O operations.
Most instructions can access only the 12 general-purpose registers r0–r11. In general, they are completely interchangeable, except that some instructions use r11 implicitly. There are also 4 base registers usable by some instructions:
* r12 = cp = Constant pool pointer
* r13 = dp = Data pointer
* r14 = sp = Stack pointer
* r15 = lr = Link register
Registers 16 through 24 are only accessible to specialized instructions. Except for the first two (r16 = pc = program counter, r17 = sr = status register), they are dedicated to exception and interrupt handling.
The status register contains various mode bits, but the processor does ''not'' have the standard ALU result flags like [[Carry flag|carry]], [[Zero flag|zero]], [[Negative flag|negative]] or [[Overflow flag|overflow]]. Add and subtract with carry instructions exist, but specify 5 operand registers: 2 inputs and input carry, and one output and output carry.
===Instruction encoding===
Instructions can use between zero and six operands. Most common arithmetic operations (such as ADD, SUB, MULT) are [[Instruction_set#Number_of_operands|three-operand instructions]] based on a set of 12 general purpose registers
Most instructions are 16 bits long and come in three forms:
# 5 bits of opcode, and up to 3 register operands specified in 11 bits, or
# 6 bits of opcode, one register specifier (4 bits) and a 6-bit unsigned immediate constant, or
# 6 bits of opcode, and 10 bits of unsigned immediate constant.
Because constants are always unsigned, many instructions come in add/subtract pairs, e.g. jump forward and backward.
In the second form, some instructions use all 4 bits to encode the register number, allowing access to r12–r15. Other instructions use those encodings for additional instructions with only one, 6-bit immediate operand.
The form of an instruction is determined by its 4 most-significant bits:
* '''00__''': 3 register operands (8 opcodes)
* '''0100''': 3 register operands (2 opcodes)
* '''0101''': register + 6-bit immediate (4 opcodes, 16 registers allowed)
* '''0110''': register + 6-bit immediate (4 opcodes, 16 registers allowed)
* '''0111''': register + 6-bit immediate (4 opcodes, 12 registers allowed)
* '''10__''': 3 register operands (8 opcodes)
* '''1100''': 3 register operands (2 opcodes)
* '''1101''': 10-bit immediate (4 opcodes)
* '''1110''': 10-bit immediate (4 opcodes)
* '''1111''': Prefix opcodes:
** '''111100''': 10 additional immediate bits, prepended to following instruction's 6 or 10 bits.
** '''11111''': 3 additional operands, in addition to the operands of the following register instruction
The encoding of the 3-operand register opcodes is quite unusual, since the number of registers is 3×4 and not a power of 2. The encoding used fits 0 to 3 operands, and the number of operands, into 11 bits. Thus, each opcode can be assigned four times, once to a 3-operand instruction, once to a 2-operand, etc.
The 3-operand form takes the low 2 bits of each register specifier and places each into a 2-bit field, using 6 bits. The high 2 bits of each operand are combined in base-3 into a number between 0 and 26 (using ''a''+3×''b''+9×''c'') and stored in the remaining 5 bits.
The 2-operand form uses the unused 5 combinations (27–31) in the 5-bit field. The 2-bit field for the low bits of operand ''a'' is reassigned; one bit is used for an additional opcode bit, and the other is used as an additional combination register specifier, allowing 10 combinations (54–63). 9 of those are assigned to encode the high bits of 2 operands (using ''b''+3×''c''+54).
1-operand instructions use the tenth combination value 63, and place the register number in the 4 available bits. (Only operand ''c'' is specified, and the high bits are stored in the ''b'' field.)
Finally, the 1-operand encoding, with a register number 12 or more (the ''b'' field contains binary 11), is also used to encode 0-operand instructions. The two low-order bits of the ''c'' field are available for additional opcode bits (bringing the total to 8).
(A few instructions use the operand number 0–11 as an immediate constant, or use it to select one of 12 convenient bit-shift
constants 0–8, 16, 24, or 32.)
Less frequently used instructions are encoded in 32 bits. These instructions encode instructions that operate on long immediate operands (far branches), on a large number of operands (for example long multiply which has 4 source and two destination operands) and instructions that are rarely used with fewer operands.
One 10-bit immediate opcode (PFIX, opcode 111100) is used to add an additional 10 bits to the 6- or 10-bit immediate in the following instruction.
One 3-operand opcode (EOPR, opcode 11111) is reserved for an "additional operands" prefix. Its 3 operands are used along with those of the following instruction word to produce additional 32-bit instructions with up to 6 operands. (2-operand 32-bit instructions also exist; those use a 2-operand form of EOPR followed by a 0-operand instruction. The extra opcode bit in the leading EOPR is used.)
==Sequential programming model==
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