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The '''XCore XS1''' is a 32-bit RISC microprocessor architecture designed by [[XMOS]]. The architecture is designed to be used in [[multi-core processor]]s for [[embedded system]]s. Each XS1 core executes up to eight concurrent threads, each thread having its own register set, and the architecture directly supports inter-thread and inter-core communication and various forms of thread scheduling.<ref>{{cite web
|title=XMOS XS1 Architecture
|format=PDF |date=07-12-2011
|url=https://www.xmos.com/
|publisher=[[XMOS]]}}
The architecture encodes instructions compactly, using 16 bits for frequently used instructions (with up to three operands) and 32 bits for less frequently used instructions (with up to 6 operands).
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