Template:Infobox CPU architecture/doc: Difference between revisions

Revision as of 01:53, 25 March 2013

Revision as of 21:51, 5 September 2015

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; encoding: Instruction set encoding, e.g. Fixed or Variable

; branching: Branching evaluation, e.g. Condition register, Condition code, Compare and branch

; endianness: Byte ordering, i.e.g. Little, Big, Bi

; page size: Primary size of page, i.e.g. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions

; extensions: ISA extensions, i.e.g. MMX, SSE, AltiVec, etc

; open: Is the architecture open or not? (as in free or proprietary)

; registers: Number and size of processor registers