Inter-processor interrupt: Difference between revisions

Content deleted Content added
No edit summary
Added some information on mechanism, operation in unix/linux systems, and a small pdf giving some information on the subject.
Line 4:
== Mechanism ==
IPI signalling is often performed through the use of the [[Advanced Programmable Interrupt Controller|APIC]]. When a CPU wishes to send an interrupt to another CPU, it stores the interrupt vector and the identifier of the target's local APIC in the Interrupt Command Register (ICR) of its own local APIC. A message is then sent via the APIC bus to the target's local APIC, which therefore issues a corresponding interrupt to its own CPU.
 
 
== Examples ==
Line 20 ⟶ 19:
 
=== Linux/Unix ===
 
In Unix/Linux, the IPI interrupt is often used by the CPU in the [[Symmetric multiprocessor|SMP]] and [[Asymmetric multiprocessing]]configurations to communicate with other processors in the configuration.