Application-specific instruction set processor: Difference between revisions

Revision as of 15:36, 16 July 2013

Revision as of 16:09, 16 July 2013

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Some ASIPs have a configurable instruction set. Usually, these cores are divided into two parts: ''static'' logic which defines a minimum ISA (instruction-set architecture) and ''configurable'' logic which can be used to design new instructions. The configurable logic can be programmed either in the field in a similar fashion to an [[FPGA]] or during the chip synthesis.

== Literature ==

* {{cite book |title=Embedded DSP Processor Design Application Specific Instruction-set Processors |author=Dake Liu |year=2008 |publisher=Elsevier Mogan Kaufmann |___location=MA |isbn=978-0-12-374123-3 }}

* {{cite book |title=Optimized ASIP Synthesis from Architecture Description Language Models |author=Oliver Schliebusch, Heinrich Meyr, Rainer Leupers |year=2007 |publisher=Springer |___location=Dordrecht |isbn=978-1-4020-5685-7 }}

* {{cite book |title=Customizable Embedded Processors |author=Paolo Ienne, Rainer Leupers (eds.) |year=2006 |publisher=Morgan Kaufmann |___location=San Mateo, CA |isbn=978-0-12-369526-0 }}

* {{cite book |title=Building ASIPs: The Mescal Methodology |author=Matthias Gries, Kurt Keutzer (eds.) |year=2005 |publisher=Springer |___location=New York |isbn=978-0-387-26057-0 }}

==External links==