Application-specific instruction set processor: Difference between revisions

Revision as of 11:16, 9 October 2013

Revision as of 11:24, 9 October 2013

Line 13:

notes the need to broaden the architectural space being

explored and to tightly couple the various subtasks in

ASIP synthesis. [[Manoj Kumar Jain et al.]] have surveyed the art of ASIP Design Space Exploration.

ASIP synthesis.

Some ASIPs have a configurable instruction set. Usually, these cores are divided into two parts: ''static'' logic which defines a minimum ISA (instruction-set architecture) and ''configurable'' logic which can be used to design new instructions. The configurable logic can be programmed either in the field in a similar fashion to an [[FPGA]] or during the chip synthesis.

== Literature ==

* {{cite Research Paperbook |title=ASIP Design Methodologies: Survey and Issues |author=Manoj Kumar Jain, M. Balakrishnan, and Anshul Kumar |year=2001 |publisher=IEEE VLSI 2001 |___location=India |issn=1063-9667 }}

* {{cite Research Paperbook |title=ASIP Design Space Exploration: Survey and Issues |author=Manoj Kumar Jain and Deepak Gour |year=20011 |publisher=IJCSIS |___location=USA |issn=1947-5500 }}

* {{cite book |title=Embedded DSP Processor Design Application Specific Instruction-set Processors |author=Dake Liu |year=2008 |publisher=Elsevier Mogan Kaufmann |___location=MA |isbn=978-0-12-374123-3 }}

* {{cite book |title=Optimized ASIP Synthesis from Architecture Description Language Models |author=Oliver Schliebusch, Heinrich Meyr, Rainer Leupers |year=2007 |publisher=Springer |___location=Dordrecht |isbn=978-1-4020-5685-7 }}