Bit-serial architecture: Difference between revisions

Revision as of 15:32, 26 October 2013

Revision as of 15:36, 26 October 2013

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In [[digital logic]] applications, '''bit-serial architectures''' send data one bit at a time, along a single wire, in contrast to [[Parallel transmission|bit-parallel]] architectures, in which data values are sent all bits at once along a group of wires.

All computers before 1951, and most of the early [[massively parallel (computing)|massive parallel processing]] machines used a bit-serial architecture -- theyarchitecture—they were [[serial computer]]s.

Bit-serial architectures were developed for [[digital signal processing]] in the 1960s through 1980s, including efficient structures for bit-serial multiplication and accumulation.<ref>

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==References==

{{reflist}}

==External links==

*[http://portal.acm.org/citation.cfm?id=503063 Application of [[FPGA]] technology to accelerate the [[finite-difference time-___domain]] (FDTD) method]

*[http://portal.acm.org/citation.cfm?id=741014 BIT-Serial [[FIR filter]]s with CSD Coefficients for FPGAs]