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* Gate delay fault
* Transition fault
* Path delay fault: This fault is due to the sum of all gate propagation delays along a single path. This fault shows that the delay of one or more paths exceeds the clock period. one major problem in finding delay faults is the number of possible paths in a circuit under test (CUT), which in the worst case can grow exponentially with the number of lines ''n'' in the circuit.
== Combinational ATPG ==
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