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Line 4: == Mechanism == ~~IPI~~On ~~signalling~~[[IBM isPC ~~often~~compatible]] ~~performed~~computers ~~through the~~that use of the [[Advanced Programmable Interrupt Controller~~\|APIC~~]] (APIC), IPI signalling is often performed using the APIC. When a CPU wishes to send an interrupt to another CPU, it stores the interrupt vector and the identifier of the target's local APIC in the Interrupt Command Register (ICR) of its own local APIC. A message is then sent via the APIC bus to the target's local APIC, which therefore issues a corresponding interrupt to its own CPU. == Examples ==

Inter-processor interrupt: Difference between revisions