They typically comprise 4 to 22 fully connected macrocells. These macrocells are typically comprisedconsist of some combinatorial logic (such as AND OR gates) and a flip-flop. In other words, a small Boolean logic equation can be built within each macrocell. This equation will combine the state of some number of binary inputs into a binary output and, if necessary, store that output in the flip-flop until the next clock edge. Of course, the particulars of the available logic gates and flip-flops are specific to each manufacturer and product family. But the general idea is always the same.
Most SPLDs use either fuses or non-volatile memory cells (EPROM, EEPROM, FLASH, and others) to define the functionality.
