Talk:Complex instruction set computer: Difference between revisions

Revision as of 19:43, 3 January 2014

Revision as of 22:29, 3 January 2014

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Instead of saying that CISC was succeeded, it would have been more accurate to have said that CISC was succeeded by RISC in the development of modern architectures, and that legacy architectures stopped executing CISC instructions directly and started breaking up the CISC instructions into RISC "micro-operations" as part of their execution. The Intel x86 and the IBM360 architectures fall in this category. The presence of these legacy architectures in desktops, servers, and mainframes is true, but I think that they are RISC systems that have a preprocessor in order to support CISC legacy code. Conceptually speaking, CISC is not a competitor to RISC for the reasons stated above. Amdahl's Law is very important in pipelining, but its general form says that the maximum expected improvement to an overall system is constrainted when only part of the system is improved. Thus devoting logic on a chip to CISC instructions is a poor choice when they are seldom used (due to compilers) and they can not be pipelined (due to widely varying execution times). Basically I think the section fails to mention that RISC won the CISC/RISC war. <span style="font-size: smaller;" class="autosigned">— Preceding [[Wikipedia:Signatures|unsigned]] comment added by [[Special:Contributions/151.151.16.22|151.151.16.22]] ([[User talk:151.151.16.22|talk]]) 19:42, 3 January 2014 (UTC)</span><!-- Template:Unsigned IP --> <!--Autosigned by SineBot-->

:Given that programmers can't write uop code for x86 or z/Architecture, and compilers can't write uop code for x86 or z/Architecture, the "legacy" architectures are still relevant.

:As for how RISCy the micro-operations are, note that, with [http://www.anandtech.com/show/1998/3 micro-operation fusion], the micro-operations aren't quite as micro; that page speaks of combining a compare instruction and a conditional branch into a single micro-op and of combining the load and add micro-ops of ADD [mem], EAX into a single micro-op. The latter is a bit of a move away from the load-store architecture aspect of RISC.

:So the only way in which RISC "won" is that the units of dispatch, scheduling, and execution in modern processors are simpler than some of the instructions in current CISC processors; the units of generated code, however, are still CISC in those processors, even if compilers only use some of the CISCy parts (memory-register and register-memory arithmetic, double-indexing in memory operands, maybe CISCier procedure calls in some cases, maybe decimal and string instructions on z/Architecture or REP/xxx instruction pairs on x86) and ignore the other CISCy parts (which don't get a lot of transistors allocated to them), and even some of the units of dispatch, scheduling, and execution might combine a memory reference and an arithmetic op (micro-operation fusion).

:The only RISC ISA that "won", for general-purpose computing, to the extent of displacing competitors or keeping them out in the first place is ARM (not a lot of Atom smartphones or tablets out there); the others lost in the desktop/laptop market (it'll be interesting to see whether ARM comes back there) and are fighting it out with x86-64 and z/Architecture in the server market. The others lost in the desktop/laptop market largely because Intel (and, to a lesser extent, AMD) had the money to throw transistors at decoders that turned x86 instructions into uop sequences; devoting logic on a chip to doing that is a very good choice if it means that you keep PowerPC, MIPS, SPARC, and PA-RISC out of a lucrative market.

:Another way to think of it is that the first "C" of "CISC" got split into "the stuff that we need to make go fast, because programmers and compilers use it a lot" and "the stuff that's not used enough, so it just has to work, not go fast", with the former stuff made to "go fast" with techniques such as breaking it into uops, and the latter stuff left around, but with the fraction of the chip used to implement it getting smaller over time. That split is a win for some of the ideas that motivated RISC, but with the "reduction" process not, for example, requiring a load-store architecture. [[User:Guy Harris|Guy Harris]] ([[User talk:Guy Harris|talk]]) 22:29, 3 January 2014 (UTC)

== instructions or operations? ==