Macrocell array: Difference between revisions

Revision as of 15:38, 5 February 2014

Revision as of 06:33, 28 March 2016

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== Macrocell arrays in ASIC ==

A '''macrocellmacrocellll array''' is an approach to the design and manufacture of [[Application-specific integrated circuit|ASIC]]s. Essentially, it is a small step up from the otherwise similar [[gate array]], but rather than being a prefabricated array of simple logic gates, the macrocell array is a prefabricated array of higher-level logic functions such as [[Flip-flop (electronics)|flip-flop]]s, [[Arithmetic logic unit|ALU]] functions, [[Hardware register|register]]s, and the like. These logic functions are simply placed at regular predefined positions and manufactured on a [[wafer (electronics)|wafer]], usually called '''master slice'''. Creation of a circuit with a specified function is accomplished by adding metal interconnects to the chips on the master slice late in the manufacturing process, allowing the function of the chip to be customised as desired.

Macrocell array master slices are usually prefabricated and stockpiled in large quantities regardless of customer orders. The fabrication according to the individual customer specifications may be finished in a shorter time compared with standard cell or [[full custom]] design. The macrocell array approach reduces the [[Photomask|mask]] costs since fewer custom masks need to be produced. In addition manufacturing test tooling lead time and costs are reduced since the same test fixtures may be used for all macrocell array products manufactured on the same [[die (manufacturing)|die]] size.