Interface logic model: Difference between revisions

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The '''Interface Logic Model''' (ILM) is a technique to model blocks in [[hierarchy|hierarchal]] [[VLSI]] [[implementation]] flow. It is a gate level [[Model (science)|model]] of a physical block where only the connections from the inputs[[input]]s to the first stage of flip-flops, and the connections from the last stage of [[Flip-flop (programming)|flip-flops]] to the outputs are in the model, including the flip-flops and the [[clock tree]] driving these flip-flops. All other internal flip-flop to flip-flop paths are stripped out of the ILM.

'''Interface Logic Model''' (ILM) is a technique to model blocks in hierarchal [[VLSI]] implementation flow.

The advantage of ILM is that the entire path ( clock to clock path) is visible at top level for [[interface]] nets, unlike traditional block -based hierarchal implementation flow. ThatThis gives better accuracy in analysis for interface nets at negligible additional [[computer memory|memory]] and [[runtime]] overhead.

It is a gate level model of a physical block where only the connections from the inputs to the first stage of flip-flops, and the connections from the last stage of flip-flops to the outputs are in the model, including the flip-flops and the clock tree driving these flip-flops. All other internal flip-flop to flip-flop paths are stripped out of the ILM.

The advantage of ILM is that entire path ( clock to clock path) is visible at top level for interface nets unlike traditional block based hierarchal implementation flow. That gives better accuracy in analysis for interface nets at negligible additional memory and runtime overhead.

[[File:Flat ilm block view vlsi 600x540.jpg]]