Multiple instruction, multiple data: Difference between revisions

Revision as of 11:51, 17 May 2014

Revision as of 04:42, 1 June 2014

Line 11:

The processors are all connected to a "globally available" memory, via either a [[software]] or hardware means. The [[operating system]] usually maintains its memory coherence.<ref name="Ibaroudene-slides">Ibaroudene, Djaffer. "Parallel Processing, EG6370G: Chapter 1, Motivation and History." Lecture Slides. [[St. Mary's University, Texas|St Mary's University]], [[San Antonio, Texas]]. Spring 2008.</ref>

From a programmer's point- of- view, this memory model is better understood than the distributed memory model. Another advantage is that memory coherence is managed by the operating system and not the written program. Two known disadvantages are: scalability beyond thirty-two processors is difficult, and the shared memory model is less flexible than the distributed memory model.<ref name="Ibaroudene-slides"/>

There are many examples of shared memory (multiprocessors): UMA ([[Uniform Memory Access]]), COMA ([[Cache Only Memory Access]]) and NUMA ([[Non-Uniform Memory Access]]).<ref name=tanenbaum>{{cite book|author=[[Andrew S. Tanenbaum]]|title=Structured Computer Organization|pages=559-585|publisher=Prentice-Hall|year=1997|url=http://cwx.prenhall.com/bookbind/pubbooks/tanenbaum2/chapter0/deluxe.html|edition=4|isbn=978-0130959904}}</ref>