Single instruction, multiple threads: Difference between revisions

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Mention Nvidia and AMD specifically
and now what it really is
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'''Single instruction, multiple thread''' (SIMT) is an [[parallel computing|parallel]] execution model, used in some [[GPGPU]] platforms, where dynamic multithreading is simulated by [[SIMD]] processors. The processors, say a number {{mvar|p}} of them, seem to be executed many more than {{mvar|p}} tasks. The threads (or tasks) are in fact partitioned into blocks that map onto the processors, and these blocks execute tasks in lock-step.<ref name="spp">{{cite book |author1=Michael McCool |author2=James Reinders |author3=Arch Robison |title=Structured Parallel Programming: Patterns for Efficient Computation |publisher=Elsevier |year=2013 |pages=209 ff.}}</ref>
'''Single instruction, multiple thread''' (SIMT) is an "execution model" and abstraction on top of the hardware paradigm, ''[[SIMD|single instruction, multiple data]]'', introduced by [[Nvidia]]:<ref>{{cite web |url=http://www.nvidia.com/content/PDF/fermi_white_papers/NVIDIA_Fermi_Compute_Architecture_Whitepaper.pdf |title=Nvidia Fermi Compute Arcitecture Whitepaper |date=2009 |website=http://www.nvidia.com/ |publisher=NVIDIA Corporation |accessdate=2014-07-17}}</ref><ref name=teslaPaper>{{cite web |url=http://dx.doi.org/10.1109/MM.2008.31 |title=NVIDIA Tesla: A Unified Graphics and Computing Architecture |date=2008 |website=http://www.ieee.org/ |publisher=IEEE |accessdate=2014-08-07 |page=6 {{subscription required|s}} }}</ref>
 
'''Single instruction, multiple thread''' (SIMT) is an "execution model" and abstraction on top of the hardware paradigm, ''[[SIMD|single instruction, multiple data]]'', introduced by [[Nvidia]]:<ref>{{cite web |url=http://www.nvidia.com/content/PDF/fermi_white_papers/NVIDIA_Fermi_Compute_Architecture_Whitepaper.pdf |title=Nvidia Fermi Compute Arcitecture Whitepaper |date=2009 |website=http://www.nvidia.com/ |publisher=NVIDIA Corporation |accessdate=2014-07-17}}</ref><ref name=teslaPaper>{{cite web |url=http://dx.doi.org/10.1109/MM.2008.31 |title=NVIDIA Tesla: A Unified Graphics and Computing Architecture |date=2008 |website=http://www.ieee.org/ |publisher=IEEE |accessdate=2014-08-07 |page=6 {{subscription required|s}} }}</ref>
 
{{Quote| [The G80 Nvidia GPU architecture] introduced the single-instruction multiple-thread (SIMT) execution model where multiple independent threads execute concurrently using a single instruction.}}
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<!-- Strictly, the latency-hiding is a feature of the zero-overhead scheduling implemented by modern GPUs... this might or might not be considered to be a property of 'SIMT' itself -->
 
A downsides of SIMT execution is the fact that control flow has to be simulated using masking: when a processor hits an ''if''-''then''-''else'' block, and its various threads execute the different paths though the block, all threads actually pass through all of the block but for processors that hit the ''if'' part the ''else'' part is "masked out", and vice versa. A benefit of it this is inexpensive synchronization.<ref name="spp">{{cite book |author1=Michael McCool |author2=James Reinders |author3=Arch Robison |title=Structured Parallel Programming: Patterns for Efficient Computation |publisher=Elsevier |year=2013 |pages=209 ff.}}</ref>
 
== See also ==