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Versions 1.0 and 1.1 of UniPro use MIPI's D-PHY technology for the off-chip Physical Layer. This PHY allows inter-chip communication. Data rates of the D-PHY are variable, but are in the range of 500-1000 Mbit/s (lower speeds are supported, but at decreased power efficiency). The D-PHY was named after the Roman number for 500 ("D").
The [[D-PHY]]<ref>[https://members.mipi.org/mipi-adopters/file-fix/Specifications/Board%20Approved/mipi_D-PHY_specification_v01-00-00.pdf MIPI Alliance Specification for D-PHY v1.00.00], requires an account at the MIPI website</ref> uses differential signaling to convey PHY symbols over micro-stripline wiring. A second differential signal pair is used to transmit the associated clock signal from the source to the destination. The D-PHY technology thus uses a total of 2 clock wires per direction plus 2 signal wires per lane and per direction. For example, a D-PHY might use 2 wires for the clock and 4 wires (2 lanes) for the data in the forward direction, but 2 wires for the clock and 6 wires (3 lanes) for the data in the reverse direction. Data traffic in the forward and reverse directions are totally independent at this level of the protocol stack.
In UniPro, the D-PHY is used in a mode (called "8b9b" encoding) which conveys 8-bit bytes as 9-bit symbols. The UniPro protocol uses this to represent special control symbols (outside the usual 0 to 255 values). The PHY itself uses this to represent certain special symbols that have meaning to the PHY itself (e.g. IDLE symbols). Note that the ratio 8:9 can cause some confusion when specifying the data rate of the D-PHY: a PHY implementation running with a 450 MHz clock frequency is often rated as a 900 Mbit/s PHY, while only 800 Mbit/s is then available for the UniPro stack.
The D-PHY also supports a Low-Power Data Transmission (LPDT) mode and various other low-power modes for use when no data needs to be sent.
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It is worth noting that UniPro supports the power efficient low speed communication modes provided by both the D-PHY (10 Mbit/s) and M-PHY (3 Mbit/sec up to 500 Mbit/s). In these modes, power consumption roughly scales with the amount of data that is sent.
Furthermore, both PHY technologies provide additional power saving modes because they were optimized for use in battery-powered devices.
==PHY Adapter Layer (L1.5)==
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[[Image:UniPro network.png|500px|thumb|Example system architecture showing multiple UniPro devices connected via UniPro switches]]
The network layer is intended to route packets through the network toward their destination. Switches within a multi-hop network use this address to decide in which direction to route individual packets. To enable this, a header containing a 7-bit destination address is added by L3 to all L2 data frames. In the example shown in the figure, this allows Device #3 to not only communicate with Device #1, #2 and #5, but also enables it to communicate with Devices #4 and #6.
Version 1.4 of the UniPro spec does not specify the details of a switch, but does specify enough to allow a device to work in a future networked environment.
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UniPro's Transport layer can be seen as providing an extra level of addressing within a UniPro device. This
* allows a UniPro device to communicate with another UniPro device using multiple logical data streams (example: sending audio and video and control information separately).
* allows a UniPro device to simultaneously connect to multiple other devices (this requires switches as supported in a [[UniPro#
* provides mechanisms to reduce the risk of congestion on the network.
* provides a mechanism to structure a stream of bytes as a stream of messages.
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==Device Management Entity (DME)==
The DME (Device Management Entity) controls the layers in the UniPro stack. It provides access to control and status parameters in all layers, manages the power mode transitions of the Link and handles the boot-up, hibernate and reset of the stack. Furthermore, it provides means to control the peer UniPro stack on the Link.
==References==
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