Automatic test pattern generation: Difference between revisions

Revision as of 00:10, 9 November 2015

Revision as of 00:10, 9 November 2015

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==== Bridging faults ====

{{main|Bridging fault}}

A short circuit between two signal lines is called bridging faults. Bridging to VDD or Vss is equivalent to stuck at fault model. Traditionally both signals after bridging were modeled with logic AND or OR of both signals. If one driver dominates the other driver in a bridging situation, the dominant driver forces the logic to the other one, in such case a dominant bridging fault is used. To better reflect the reality of CMOS VLSI devices, a Dominant AND or Dominant OR bridging fault model is used. in In the latter case, dominant driver keeps its value, while the other one gets the AND or OR value of its own and the dominant driver.

==== Opens faults ====