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Added principle of operation of DRAM read and DRAM write with illustrations. |
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'''DRAM''' is a type of [[random access memory]] that stores each [[bit]] of data in a separate [[capacitor]]. The amount of electric charge stored in the capacitor determines whether the bit is considered 1 or 0. As leakage causes the charge on a capacitor to decay, the information gets lost eventually, unless the charge is refreshed periodically. This puts DRAM in the class of ''volatile'' memory devices.
[[Image:square_array_of_mosfet_cells_read.png|left|200px|DRAM read]]
[[Image:square_array_of_mosfet_cells_read.png|right|200px|DRAM write]]
==Principle of operation of DRAM==
DRAM is usually arranged in a square array of capacitors (actually MOSFETs with big drain capacitances), as shown in the illustrations here which show a simple example with only 4 by 4 cells (more typical DRAM has 1024 by 1024 cells). During a read of any cell, the entire row is read out and written back in (refresh). During a write to a particular cell, the entire row is read out, one value changed, and then the entire row is written back in, as illustrated in the figure to the right.
[[Refresh logic]] is commonly used with DRAMs to automate the periodic refresh. This makes the circuit more complicated, but the drawback is usually outweighed by the fact that capacitors are cheap and small, so high-density, low-power memory chips can be made using this technology. The alternative to DRAM is [[Static Random Access Memory|SRAM]].
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