Dynamic random-access memory: Difference between revisions

Revision as of 17:24, 5 November 2004

Revision as of 05:39, 11 November 2004

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[[Image:square_array_of_mosfet_cells_write.png|thumb|right|200px|DRAM write]]

==Principle of operation of DRAM==

DRAM is usually arranged in a square array of capacitors (actually MOSFETs with big drain capacitances), as shown in the illustrations here which show a simple example with only 4 by 4 cells (more typical DRAM has 1024 by 1024 cells). During a read of any cell, the entire row is read out and written back in (refresh). During a write to a particular cell, the entire row is read out, one value changed, and then the entire row is written back in, as illustrated in the figure to the right.

[[Refresh logic]] is commonly used with DRAMs to automate the periodic refresh. This makes the circuit more complicated, but the drawback is usually outweighed by the fact that capacitors are cheap and small, so high-density, low-power memory chips can be made using this technology. The alternative to DRAM is [[Static Random Access Memory|SRAM]].