Dynamic random-access memory: Difference between revisions

Revision as of 05:39, 11 November 2004

Revision as of 05:44, 11 November 2004

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DRAM is usually arranged in a square array of capacitors, as shown in the illustrations here which show a simple example with only 4 by 4 cells (more typical DRAM has 1024 by 1024 cells). During a read of any cell, the entire row is read out and written back in (refresh). During a write to a particular cell, the entire row is read out, one value changed, and then the entire row is written back in, as illustrated in the figure to the right.

[[Refresh logic]] is commonly used with DRAMs to automate the periodic refresh. This makes the circuit more complicated, but the drawback is usually outweighed by the fact that capacitors are cheap and small, so high-density, low-power memory chips can be made using this technology. TheA common alternative to DRAM is [[Static Random Access Memory|SRAM]] which does not require explicit refresh.

== DRAM Interface ==

An important feature of DRAMs is called ''address multiplexing''. This technique splits the address in half and feeds each half in turn to the chip on the same set of pins. ThereforeMany a[[microprocessor]]s DRAMinclude needscontrol onlylogic halffor asDRAMs, manyrelieving addressthe pinscircuit asdesigner an SRAM offrom the same capacity, allowing itneed to beprovide produced in a smaller, cheaperaddress multiplexing packagelogic.

The ''addressAddress multiplexing'' mentioned above is the key to understanding DRAM. The chip has a large array of memory capacitors that are arranged in rows and columns. To read one ___location in the array, the control circuit first calculates its row number, which it places on the DRAM's address pins. It then toggles the ''row address select (RAS)'' pin, causing the DRAM to read the row address. Internally, the DRAM connects the selected row to a bank of [[amplifier]]s called sense amplifiers, which read the contents of all the capacitors in the row. The control circuit then places the column number of the desired ___location on the same address pins, and toggles the ''column address select (CAS)'' pin, causing the DRAM to read the column address. The DRAM uses this to select the output of the sense amplifier corresponding to the selected column. After a delay called the ''CAS access time'', this output is presented to the outside world on the DRAM's data I/O pin.

Many [[microprocessor]]s include control logic for DRAMs, relieving the circuit designer from the need to provide address multiplexing logic.

== Designing with DRAM ==

The ''address multiplexing'' mentioned above is the key to understanding DRAM. The chip has a large array of memory capacitors that are arranged in rows and columns. To read one ___location in the array, the control circuit first calculates its row number, which it places on the DRAM's address pins. It then toggles the ''row address select (RAS)'' pin, causing the DRAM to read the row address. Internally, the DRAM connects the selected row to a bank of [[amplifier]]s called sense amplifiers, which read the contents of all the capacitors in the row. The control circuit then places the column number of the desired ___location on the same address pins, and toggles the ''column address select (CAS)'' pin, causing the DRAM to read the column address. The DRAM uses this to select the output of the sense amplifier corresponding to the selected column. After a delay called the ''CAS access time'', this output is presented to the outside world on the DRAM's data I/O pin.

To write data to the DRAM, the control logic uses the same two-step addressing method, but instead of reading the data from the chip at the end of the operation, it provides data to the chip at the start of the operation.