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==Implementation techniques==
There are many architectural techniques employed to reduce the overall latency for a single computing task. These typically involve adding additional hardware in the [[Pipeline_(computing)|pipeline]] to serve instructions as soon as they are fetched from [[Random-access_memory|memory]] or [[CPU cache|instruction cache]]. A notable characteristic of these architectures is that a significant area of the chip is used up in parts other than the [[Execution_unit|Execution Units]] themselves. This is because the intent is to bring down the time required to complete a 'typical' task in a computing environment. A typical computing task is a serial set of instructions, where there is a high dependency on results produced by the previous instructions of the same task. Hence, it makes sense that the microprocessor will be spending its time doing many other tasks other than the calculations required by the individual instructions themselves. If the [[Hazard_(computer_architecture)|hazards]] encountered during computation are not resolved quickly, then latency for the thread increases. This is because hazards stall execution of subsequent instructions and, depending upon the pipeline implementation, may either stall progress completely until the dependency is resolved or lead to an avalanche of more hazards in future instructions; further exacerbating execution time for the thread.<ref name="quant">{{cite book|author1=John L. Hennessy |author2=David A. Patterson |title=Computer Architecture: A Quantitative Approach |edition=Fifth Edition |year=2013 |publisher=Morgan Kaufmann Publishers |isbn=012383872X}}</ref><ref name="interface">{{cite book|
The design space of micro-architectural techniques is very large. Below are some of the most commonly employed techniques to reduce the overall latency for a thread.
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