XCore Architecture: Difference between revisions

Revision as of 11:10, 28 December 2016

Revision as of 15:06, 3 January 2017

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{{Infobox CPU architecture

| name = XCore XS1, XCore XS2

| designer = [[XMOS]]

| bits = 32-bit

| introduced = 2007

| version = XS1, XS2

| design = [[RISC]]

| type = [[Load-store architecture|Load-store]]

| encoding = Variable

| branching = Condition register

| endianness = Little

| gpr = 12

| fpr = 0

}}

{{Infobox CPU architecture

| name = XCore XS2

| designer = [[XMOS]]

| bits = 32-bit

| introduced = 2015

| version = XS2

| design = [[RISC]]

| type = [[Load-store architecture|Load-store]]