XCore Architecture: Difference between revisions

Revision as of 15:06, 3 January 2017

Revision as of 04:05, 13 January 2017

Line 20:

|date=2016-12-21

|url=https://www.xmos.com/published/xmos-xs1-architecture?format=pdf

|publisher=[[XMOS]]}}</ref> and the XS2 architecture.<ref name='"xs2'">{{cite web

|title=xCORE-200: The XMOS XS2 Architecture

|format=PDF

Line 43:

The XS2 architecture was defined in 2015. It is implemented by the [[xCORE-VOICE]] processors and [[xCORE-200]] series processors. The latter are marketed as the XL2 series (general purpose), XU2 series (USB), XE2 series (RGMII), and versions with embedded flash.

XS2 extends the XS1 architecture with a limited form of [[Dual Issue]] execution.<ref name='"xs2'"/> The processor core comprises two lanes. The ''Resource lane'' can execute IO operations and general arithmetic. The ''Memory lane'' can execute memory operations, branches, and general arithmetic. Short resource or arithmetic instructions can be executed in the resource lane; short memory, branch, or arithmetic operations can be executed in the memory lane. Long instructions span both lanes. In dual issue mode all pairs of instructions are aligned on a 32-bit boundary.

A few instructions have been added to aid in high bandwidth processing, such as dual-word load/store, dual-word zip and unzip (bit and byte strings), dual word arithmetic saturation and shift.

Line 76:

|colspan=5| opcode ||colspan=5| 9×''a''+3×''b''+''c'' ||colspan=2| a a ||colspan=2| b b ||colspan=2| c c ||align=left| three-operand register

|-

|colspan=5| opcode ||colspan=5| 27+3×''b''+''c'' || '''&lowast;∗''' || o ||colspan=2| b b ||colspan=2| c c ||align=left| two-operand register

|-

|colspan=5| opcode ||colspan=6| 1 1 1 1 1 1 || o ||colspan=4| c c c c ||align=left| one-operand register