Multiprocessor: Difference between revisions

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A system with more than one processor .<ref>http://www.cs.vu.nl/~ast/books/mos2/sample-8.pdf</ref>.

There are many types of '''multiprocessor''' systems. These can be classified based on:

* Loosely coupled vs tightly coupled multiprocessor system

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* UMA vs cc-NUMA system

* Hybrid system - shared system memory for global data and local memory for local data

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== Loosely coupled multiprocessor system ==

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[[File:Loosely Coupled Multiprocessor System.svg|thumb|right|upright=1.8|Loosely Coupled Multiprocessor System]]

In a distributed memory multiprocessor system, each processor has its local memory, IO channels and with an independent [[operating system]]. Processors can exchange data through a high-speed interconnection network by means of communication through the [[message passing]]

=== System characteristics ===

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* These systems are capable of processing multiple instruction, multiple data (MIMD) programming

* This type of architecture allows [[parallel computing|parallel processing]].

* The distributed memory allows high scalability

== Tightly coupled multiprocessor system ==

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([[Symmetric Multiprocessor System|SMP]])

Systems operating under a single OS (Operating System) with two or more homogeneous processors and with a centralized shared Main Memory.

[[File:SMP - Symmetric Multiprocessor System.svg|thumb|right|upright=1.8|Symmetric Multiprocessor System]]

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[[File:cc-NUMA System.svg|thumb|right|upright=2|cc-NUMA System]]

It is known that the SMP system is limited in scalability.

To overcome this limitation, the architecture called "'''''cc-NUMA '''''" is normally used.

cc-NUMA system is a cluster of SMP systems, called "'''NODEs'''", connected via a high-speed ''connection network'' that can be a ''link'' that can be a single or double-reverse ring, or multi-ring, point-to-point connections<ref>AMD Opteron Shared Memory MP Systems – http://www.cse.wustl.edu/~roger/569M.s09/28_AMD_Hammer_MP_HC_v8.pdf</ref><ref>An Introduction to the Intel® QuickPath Interconnect – http://www.intel.ie/content/dam/doc/white-paper/quick-path-interconnect-introduction-paper.pdf </ref> or a mix of these (e.g. [[IBM Power Systems]]<ref>AMD Opteron Shared Memory MP Systems – http://www.cse.wustl.edu/~roger/569M.s09/28_AMD_Hammer_MP_HC_v8.pdf</ref><ref>[https://computing.llnl.gov/tutorials/ibm_sp/ IBM POWER Systems Overview]</ref>), bus interconnection (e.g. NUMAq<ref>SourceForge – http://lse.sourceforge.net/numa/faq/system_descriptions.html</ref>), ''crossbar'', ''segmented bus'' ([[Non-uniform memory access|NUMA]] Bull HN ISI ex [[Honeywell]]<ref>Bull HN F. Zulian – A. Zulian patent – Computer system with a bus having a segmented structure – http://www.freepatentsonline.com/6314484.html</ref>), ''[[Mesh networking|Mesh router]]'', etc..

The main characteristic of cc-NUMA system is to have an unique shared global memory distributed in each node

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Each node usually is a SMP system, where a processor can be a single processor or a multi-core processor or mix of this two or any other kind of architecture. The fig. aside is just an example.

The difference in access time from local and remote can be also of an order of magnitude, depending on the kind of the connection network used (faster in segmented bus, crossbar and point-to-point interconnection, slower in serial rings connection).

To overcome this limit a large remote cache (see [[Cache memory#Directory-based cache coherence – message-passing|Remote cache]]) is normally used. With this solution the cc-NUMA system become very close to a large SMP system.

== Tightly coupled vs Loosely coupled architecture ==

Both architectures have advantages and trade offs which may be summarized as follows:

* Loosely coupled architectures feature high performances of each individual processor but do not enable for an easy real time balancing of the load among processors.

* Tightly coupled architectures feature by reverse an easy load balancing and distribution among processors but suffer from the bottleneck consisting in the sharing of common resources through one or more buses (which is also a common resource)

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An intermediate approach of the two previous architectures, is one having common resources and local resources such as local memories (LM) in each processor. The common resources are accessible to all the processors through the system bus and the local resources being accessible to the pertaining processor. Cache memories, may be viewed in this perspective as local memories

.

This system (patented F. Zulian <ref>http://www.google.ch/patents/US4928224</ref>) used on the DPX/2 300 Unix based system (Bull Hn Information Systems Italia (ex Honeywell)) ,<ref>http://www.feb-patrimoine.com/english/unix_and_bull.htm</ref><ref>http://www.feb-patrimoine.com/english/bull_dpx2.htm</ref>, is a mix of tightly coupled and loose coupled systems and takes all the advancements of these two architectures

The Local memory is divided into two sectors, global data (GD) and local data (LD).