'''[[Dual Channel]]''' memory controllers are memory controllers where the DRAM devices are separated onto two different busses to allow two memory controllers to access them in parallel. This doubles the theoretical amount of bandwidth of the bus. In theory, more channels can be built (a channel for every DRAM cell would be the ideal solution), but due to wire count, [[Crosstalk (electronics)|line capacitance]], and the need for parallel access lines to have identical lengths, more channels are very difficult to add.
==Fully- buffered memory==
'''Fully- buffered memory''' systems places a memory buffer device on every [[DIMM|memory module]] (called an [[FB-DIMM]] when Fully Buffered RAM is used), which unlike traditional memory controller devices, uses a serial data link to the memory controller instead of the parallel link used in previous RAM designs. This decreases the number of the wires necessary to place the memory devices on a motherboard (allowing for a smaller number of layers to be used, meaning more memory devices can be placed on a single board), at the expense of increasing latency (the time necessary to access a memory ___location). This increase is due to the time required to convert the parallel information read from the DRAM cell to the serial format used by the FB-DIMM controller, and back to a parallel form in the memory controller on the motherboard. In theory, the FB-DIMM's memory buffer device could be built to access any DRAM cells, allowing for memory cell agnostic memory controller design, but this has not been demonstrated, as the technology is in its infancy.
