Bit-serial architecture: Difference between revisions

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All computers before 1951, and most of the early [[massively parallel (computing)|massive parallel processing]] machines used a bit-serial architecture—they were [[serial computer]]s.

Bit-serial architectures were developed for [[digital signal processing]] in the 1960s through 1980s, including efficient structures for bit-serial multiplication and accumulation.<ref name="Denyer_1995"/>

{{cite book

| title = VLSI signal processing: a bit-serial approach

| author = [[Peter B. Denyer]] and David Renshaw

| publisher = Addison-Wesley

| year = 1985

| isbn = 978-0-201-13306-6

| url = http://www.google.com/search?tbm=bks&tbo=1&q=intitle%3A%22bit-serial%22+jackson+kaiser+macdonald&btnG=Search+Books#sclient=psy&hl=en&tbo=1&tbm=bks&source=hp&q=intitle:%22bit-serial%22+jackson+kaiser+mcdonald&aq=f&aqi=&aql=&oq=&pbx=1&bav=on.2,or.r_gc.r_pw.&fp=93266f80b0a6b0fe&biw=1261&bih=660

}}</ref>

Often N serial processors will take less FPGA area and have a higher total performance than a single N-bit parallel processor.

==See also==

*[https://bitserial.io?sp=optional BIT SERIAL ICO PLAN]

*[[1-bit architecture]]

*[[Bit slicing]]

*[[Digit-serial architecture]]<!-- with possibilties -->

==References==

{{reflist}}|refs=

<ref name="Denyer_1995">

{{cite book |title=VLSI signal processing: a bit-serial approach |series=VLSI systems series |author-first1=Peter B. |author-last1=Denyer |author-link1=Peter B. Denyer |author-first2=David |author-last2=Renshaw |publisher=[[Addison-Wesley]] |date=1985 |isbn=978-0-201-13306-6 |url=https://books.google.com/books/about/VLSI_signal_processing.html?id=EklTAAAAMAAJ}}</ref>

}}

==External links==

* [http://portal.acm.org/citation.cfm?id=503063 Application of [[FPGA]] technology to accelerate the [[finite-difference time-___domain]] (FDTD) method]

* [http://portal.acm.org/citation.cfm?id=741014 BIT-Serial [[FIR filter]]s with CSD Coefficients for FPGAs]

{{CPU technologies}}