Parallel Element Processing Ensemble: Difference between revisions

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The '''Parallel Element Processing Ensemble''' (also known as '''PEPE''') was one of the very early [[parallel computing]] systems. Bell began researching the concept in the mid-1960s as a way to provide high -performance computing support for the needs of [[anti-ballistic missile]] (ABM) systems. The goal was to build a computer system that could simultaneously track uphundreds to 288of incoming [[ballistic missile]] [[warhead]]s.<ref name=silogic>[http://www.silogic.com/PEPE/PEPE.html PEPE - Parallel Element Processing Ensemble] Last updated on June 8, 2011.</ref><ref name=Ford>{{cite book|author=R. Michael Ford|title=Parallel supercomputing in SIMD architecture|edition=1st|publisher=CRC Press|year=1990|page=7|isbn=0-8493-4271-6}}</ref><ref>[http://www.dtic.mil/cgi-bin/GetTRDoc?Location=U2&doc=GetTRDoc.pdf&AD=AD0911667 Real-Time Advanced Data Processing Parallel Element Processing Ensemble (PEPE)], June 30, 1973, Final Report for Contract DAHC60-72-C-0031, prepared by the System Development Corporation of Huntsville, Alabama for the U.S. Army Advanced Ballistic Missile Defense Agency.</ref> A single PEPE system was built by [[Burroughs Corporation]] in the 1970s, by which time the [[US Army]]'s ABM efforts were winding down. The design later evolved into the [[Burroughs Scientific Computer]] for commercial sales, but a lack of sales prospects led to it being withdrawn from the market.

PEPE came about as a result of predictions of the sorts of ICBM forces that would be expected in the event of an all-out Soviet attack during the 1970s. Missile fleets of both the US and USSR were growing through the 1960s, but a bigger issue was the number of warheads as a result of the move to [[multiple independently targetable reentry vehicle]]s]s (MIRV). Computers designed for the [[Nike-X]] system were largely similar to systems like the [[IBM 7030]], and would have been able to handle attacks with perhaps a dozen warheads arriving simultaneously. With MIRV, hundreds of targets, both warheads and decoys, would arrive at the same time, and the CPUs being used simply did not have the performance needed to analyze their trajectories quickly enough to leave time to attack them.

An initial testbed system, the "IC model", was built with 16 processors consisting of individual [[integrated circuit]]s and connected to an [[IBM 360]]/65 host. This proved successful, and Burroughs won the contract to build a prototype of the full-sized 288-processor version in the early 1970s. The design featured an array of 288 (8 × 36) identical processing elements and [[Content-addressable memory|associative addressing]]. Each processing element contained a minimum of control logic, the bulk of the control being concentrated in a common control unit. The control unit read instructions from memory, decoded them, and issued them to all processing elements simultaneously so that the elements were required to execute exactly the same instruction at exactly the same time. The elements were capable of executing a complete single address instruction repertoire permitting any desired arithmetic or logical operation.