Hardware-based encryption: Difference between revisions

Revision as of 03:56, 24 January 2018

Revision as of 03:57, 24 January 2018

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==== [[x86]] ====

{{Main|AES instruction set|Intel SHA extensions}}

The X86 [[Computer architecture|architecture]], as a [[Complex instruction set computer|CISC (Complex Instruction Set Computer)]] Architecture, typically implements complex [[algorithms]] in hardware. Cryptographic algorithms are no exception. The x86 architecture implements significant components of the [[Advanced Encryption Standard|AES (Advanced&nbsp;Encryption&nbsp;Standard)]] algorithm, which can be used by the [[NSA]] for [[Top Secret]] information.<ref>{{cite web|url=http://csrc.nist.gov/groups/ST/toolkit/documents/aes/CNSS15FS.pdf |title=National Policy on the Use of the Advanced Encryption Standard (AES) to Protect National Security Systems and National Security Information |author=Lynn Hathaway |date={{date|June 2003}}|format=PDF |access-date={{date|2011-02-15}}}}</ref> The architecture also includes support for the [[Secure Hash Algorithms|SHA]] Hashing Algorithms through the [[Intel SHA extensions]].<ref name="Intel AES Instructions" /> Whereas AES is a cipher, which is useful for encrypting documents, [[Hash function|Hashing]] is used for verification, such as of passwords (see [[PBKDF2]]).

==== ARM ====

ARM processors can optionally support Security Extensions. Although ARM is a [[RISC|RISC (Reduced Instruction Set Computer)]] architecture, there are several optional extensions specified by [[ARM Holdings]].<ref name="cortex cryptography" /><ref name="openwrt">[http://wiki.openwrt.org/doc/hardware/cryptographic.hardware.accelerators Cryptographic Hardware Accelerators] on OpenWRT.org</ref>