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In fact, because the program counter is always word-aligned the lowest two bits are always zero which allowed the designers to reuse these two bits to hold the processor's mode bits too. The four modes allowed were USR26, SVC26, IRQ26, FIQ26; contrast this with the 32 possible modes available when the program status was separated from the program counter in more recent [[ARM architecture]]s.
This design enabled more efficient [[Computer_program|program]] execution, as the Program Counter and status flags could be saved and restored with a single operation.{{Citation needed|date=July 2019}} This resulted in faster [[subroutine]] calls and [[interrupt]] response than traditional designs, which would have to do two register loads or saves when calling or returning from a subroutine.
Despite having a [[32-bit]] ALU and word-length, processors based on ARM architecture version 1 and 2 had only a 26-bit PC and [[address bus]], and were consequently limited to 64 MiB of addressable [[Random Access Memory|memory]]. This was still a vast amount of memory at the time, but because of this limitation, architectures since have included various steps away from the original 26-bit design.
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