FPGA prototyping: Difference between revisions

Revision as of 19:10, 7 October 2018

Revision as of 04:43, 8 October 2018

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#Development Cost: Development cost of 90-nm ASIC/SoC design tape-out is around $20 million, with a mask set costing over $1 million alone.<ref name= soc/> Development costs of 45-nm designs are expected to top $40 million. With increasing cost of mask sets, and the continuous decrease of IC size, minimizing the number of re-spins is vital to the development process.

==Design for Prototypingprototyping==

'''Design for Prototyping'''<ref>{{cite web|url=http://www.newelectronics.co.uk/electronics-technology/prototyping-system-designs-on-fpgas/32395/|title=Prototyping System Designs on FPGAs|last=|first=|date=2011-03-22|website=|publisher=New Electronics|archive-url=|archive-date=|dead-url=|accessdate=2011-03-22}}</ref> ('''DFP''') refers to designing systems that are amenable to [[prototyping]]. Many of the obstacles facing development teams who adopt FPGA prototypes can be distilled down to three "laws":

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Putting a SoC design into an FPGA prototype requires careful planning in order to accomplish prototyping goals with minimal effort. To ease the development of the prototype, best practices called, Design-for-Prototyping, influences both the [[System on a chip#Design flow|SoC design]] style and the project procedures applied by design teams. Procedural recommendations include adding DFP conventions to RTL coding standards, employing a prototype compatible simulation environment, and instituting a system debug strategy jointly with the software team.

==Partitioning Issuesissues==

Due to increased circuit complexity, and time-to-market shrinking, the need for verification of application-specific-integrated-circuit (ASIC) and system-on-chip (SoC) designs is growing. Hardware platforms are becoming more prominent amongst verification engineers due to the ability to test system designs at-speed with on-chip bus clocks, as compared to simulation clocks which may not provide an accurate reading of system behavior.<ref>{{Cite news|url=http://www.eejournal.com/archives/articles/20110825-mathworks/|title=Best Practices for FPGA Prototyping of MATLAB and Simulink Algorithms|date=2011-08-25|work=EEJournal|access-date=2018-10-08|language=en-US}}</ref> These multi-million gate designs usually are placed in a multi-FPGA prototyping platform with six or more FPGAs, since they are unable to fit entirely onto a single FPGA. The fewer number of FPGAs the design has to be partitioned to reduces the effort from the design engineer.<ref name= Aldec/> To the right is a picture of a FPGA-based prototyping platform utilizing a dual-FPGA configuration. [[File:Aldec HES7 ASIC Prototyping Platform.jpg|thumb|alt=Aldec FPGA-based prototyping platform with dual FPGA configuration.|Aldec's HES-7 ASIC prototyping solution]]

System RTL designs or netlist’snetlists will have to be partitioned onto each FPGA to be able to fit the design onto the prototyping platform.<ref>http://www.electronicsweekly.com/Articles/20/12/2007/42539/fpga-prototyping-its-about-the-software.htm</ref> This introduces new challenges for the engineer since manual partitioning requires tremendous effort and frequently results in poor speed (of the design under test).<ref name ="Aldec">[http://www.aldec.com/en/downloads/private/284 "Aldec and Xilinx Co-Authored White Paper "HES-7 ASIC Prototyping"], Registration Required</ref> If the number or partitions can be reduced or the entire design can be placed onto a single FPGA, the implementation of the design onto the prototyping platform becomes easier.

===Balance FPGA Resources While Creating Design Partitions<ref name = Aldec/>===

When creating circuit partitions, engineers should first observe the available resources the FPGA offers, since the design will be placed onto the FPGA fabric.<ref name="Aldec" /> The architecture of each FPGA is dependent on the manufacturer, but the main goal in design partitioning is to have an even balance of FPGA resource utilization. Various FPGA resources include [[Lookup table|lookup tables]] (LUTs), [[D flip-flops]], block [[Random-access memory|RAMs]], [[Digital signal processor|digital signal processors]] (DSPs), clock buffers, etc. Prior to balancing the design partitions, it is also valuable to the user to perform global logic optimization to remove any redundant or unused logic. A typical problem that arises with creating balanced partitions is that it may lead to timing or resource conflict if the cut is on many signal lines. To have a fully optimized partitioning strategy, the engineer must consider issues such as timing/power constraints and placement and routing while still maintaining a balanced partition amongst the FPGAs. Strictly focusing on a single issue during a partition may create several issues in another.

===Placing and Routing Partitions===

In order to achieve optimal place and routing for partitioned designs, the engineer must focus on FPGA pin count and inter-FPGA signals. After partitioning the design into separate FPGAs, the number of inter-FPGA signals must not to exceed the pin count on the FPGA.<ref>http://www.fpga-faq.com/FAQ_Pages/prototyping.pdf</ref> This is very difficult to avoid when circuit designs are immense, thus signals must utilize strategies such as [[time-division- multiplexing]] (TDM) which multiple signals can be transferred over a single line.<ref>{{Cite web|url=http://www.inetdaemon.com/tutorials/telecom/t-carrier/time-division_multiplexing.shtml|title=Time-Division Multiplexing|website=www.inetdaemon.com|language=en-US|access-date=2018-10-08}}</ref> These multiple signals, called sub-channels, take turns being transferred over the line over a time slot. When the TDM ratio is high, the bus clock frequency has to be reduced to accommodate time slots for each sub-channel. By reducing the clock frequency the throughput of the system is hindered.<ref name=Aldec/>

===Timing Requirements===