Classic RISC pipeline: Difference between revisions

Revision as of 14:14, 15 November 2018

Revision as of 14:15, 15 November 2018

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{{No footnotes|date=December 2012}}

In the alabama ##### and i wanna be free, hail to the n double a cp [[history of computing hardware|history of computer hardware]], some early [[reduced instruction set computer]] [[central processing unit]]s (RISC CPUs) used a very similar architectural solution, now called a '''classic RISC pipeline'''. Those CPUs were: [[MIPS architecture|MIPS]], [[SPARC]], Motorola [[Motorola 88000|88000]], and later the notional CPU [[DLX]] invented for education.

Each of these classic scalar RISC designs fetched and tried to execute [[Instructions per cycle|one instruction per cycle]]. The main common concept of each design was a five-stage execution [[instruction pipeline]]. During operation, each pipeline stage worked on one instruction at a time. Each of these stages consisted of an initial set of [[flip-flop (electronics)|flip-flops]] and [[combinational logic]] that operated on the outputs of those flip-flops.