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Guy Harris (talk | contribs) →King John question: "It's complicated", but there is no reason to label all architectures that support self-modifying code on at least one OS as being "modified" von Neumann architectures. |
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:I don't see "von Neumann" anywhere in the article, but I think that the relationship is that the [[von Neumann architecture]] envisaged a computer with a single memory space comprising both data and instructions. Self-modifying code would require that a program be able to treat a piece of memory as data and then reach it as an instruction, and would not be possible on a non-von Neumann computer with, for example, separate code and data spaces. (Who is King John?) [[User:Spike-from-NH|Spike-from-NH]] ([[User talk:Spike-from-NH|talk]]) 00:26, 25 April 2012 (UTC)
::I'm not sure what a "modified" von Neumann architecture is; a [[modified Harvard architecture]] could be one of at least three types:
::*an architecture with one address space for both instructions and data, but with separate instruction and data caches and separate buses between the CPU and the two caches, i.e. what the "modified Harvard architecture" page calls a "[[modified Harvard architecture#Split-cache (or almost-von-Neumann) architecture|split-cache architecture]]";
::*an architecture with separate address spaces for instructions and data, but with instructions that allow fetches from, or stores into, the instruction address space, i.e. what the "modified Harvard architecture" page calls a "[[modified Harvard architecture#Instruction-memory-as-data architecture|instruction-memory-as-data architecture]]";
::*an architecture like that of the [[Maxim Integrated]] MAXQ family of processors, which the "modified Harvard architecture" page calls a "[[modified Harvard architecture#Data-memory-as-instruction architecture|data-memory-as-instruction architecture]], and which is not exactly easy to explain (MAXQ is ''different'').
::The only one of those that I might call a "modified von Neumann architecture" would be the first of them, as, for the vast majority of operations, it is indistinguishable from an ''un''modified von Neumann architecture. The primary difference visible to most user-mode code is that, on ''some'' such architectures, stores must ensure that all caches, whether instruction, data, or unified, be updated or flushed (this is the case on [[x86]], for backwards compatibility with older processors without any caches or with only a unified cache) and, on others, a store is not guaranteed to flush instruction caches, and the architecture defines an instruction or instructions to force a flush, and attempts to execute the code being modified are not guaranteed to work correctly until after the instruction completes (this is the case on [[SPARC]], for example).
::In the case of x86, I think there ''might'' be instruction-pipeline issues that require some care when modifying code, dating all the way back to the [[8086]]; a case could perhaps be made that ''any'' architecture on which there is no guarantee that casually storing into the instruction stream will Just Work is a "modified von Neumann architecture", even if it's not a "modified Harvard architecture" in the sense of "it has, at some level, separate buses for fetching instructions and data, even though code and data are in the same address space and the same physical memory".
::So I don't see any way in which "any hardware that can allow self-modifying code to run in at least one operating system" is required to be "a "modified von Neumann architecture" computer" - no modification to the von Neumann architecture is necessary to support that. A particular architecture might be "modified" in the sense that it requires that care be taken when storing into code space, but an architecture could also require that no code need be taken, and require implementations to do whatever is necessary to make that be the case.
::I.e., being a von Neumann architecture in the address-space sense is sufficient; a "split-cache architecture" is a pure or modified von Neumann architecture in the address-space sense, and a modified Harvard architecture in the "bus between the CPU and the lowest level of caches" sense.
::Even the other flavors of modified Harvard architecture could conceivably support self-modifying code. [[User:Guy Harris|Guy Harris]] ([[User talk:Guy Harris|talk]]) 07:22, 15 May 2022 (UTC)
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