Reconfigurable computing: Difference between revisions

Revision as of 14:48, 14 January 2019

Revision as of 01:10, 7 February 2019

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''Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines''

(FCCM '97, April 16–18, 1997), pp. 24–33.

</ref> Elixent, NGEN,<ref>{{Cite journal|last=McCaskill|first=John S.|last2=Chorongiewski|first2=Harald|last3=Mekelburg|first3=Karsten|last4=Tangen|first4=Uwe|last5=Gemm|first5=Udo|date=1994-09-01|title=NGEN — Configurable computer hardware to simulate long-time self-organization of biopolymers|url=http://onlinelibrary.wiley.com/doi/10.1002/bbpc.19940980906/abstract|journal=Berichte der Bunsengesellschaft für physikalischePhysikalische Chemie|language=en|volume=98|issue=9|pages=1114–11141114|doi=10.1002/bbpc.19940980906|issn=0005-9021}}</ref> Polyp,<ref>{{Cite book|url=https://www.worldcat.org/oclc/39655211|title=Evolvable systems : from biology to hardware : second International Conference, ICES 98, Lausanne, Switzerland, September 23-25, 1998 : proceedings|date=1998|publisher=Springer|others=Sipper, Moshe., Mange, Daniel, 1940-, Pérez-Uribe, Andrés., International Conference on Evolvable Systems (2nd : 1998 : Lausanne, Switzerland)|isbn=3540649549978-3540649540|___location=Berlin|oclc=39655211}}</ref> MereGen,<ref name=":1">{{Cite book|url=https://www.worldcat.org/oclc/49750250|title=Coupling of biological and electronic systems : proceedings of the 2nd Caesarium, Bonn, November 1-3, 2000|date=2002|publisher=Springer|others=Hoffmann, K.-H. (Karl-Heinz)|isbn=3540436995978-3540436997|___location=Berlin|oclc=49750250}}</ref> PACT XPP, Silicon Hive, Montium, Pleiades, Morphosys, and PiCoGA.<ref>Campi, F.; Toma, M.; Lodi, A.; Cappelli, A.; Canegallo, R.; Guerrieri, R., "A VLIW processor with reconfigurable instruction set for embedded applications", Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International, vol., no., pp. 250–491 vol. 1, 2003</ref> Such designs were feasible due to the constant progress of silicon technology that let complex designs be implemented on one chip. Some of these massively parallel reconfigurable computers were built primarily for special subdomains such as molecular evolution, neural or image processing. The world's first commercial reconfigurable computer, the Algotronix CHS2X4, was completed in 1991. It was not a commercial success, but was promising enough that [[Xilinx]] (the inventor of the [[FPGA|Field-Programmable Gate Array]], FPGA) bought the technology and hired the Algotronix staff.<ref>[http://www.algotronix.com/people/tom/album.html Algotronix History]</ref> Later machines enabled first demonstrations of scientific principles, such as the spontaneous spatial self-organisation of genetic coding with MereGen.<ref>{{Cite journal|last=Füchslin|first=Rudolf M.|last2=McCaskill|first2=John S.|date=2001-07-31|title=Evolutionary self-organization of cell-free genetic coding|url=http://www.pnas.org/content/98/16/9185|journal=Proceedings of the National Academy of Sciences|language=en|volume=98|issue=16|pages=9185–9190|doi=10.1073/pnas.151253198|issn=0027-8424|pmc=55395|pmid=11470896}}</ref>

==Theories==

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This heterogeneous systems technique is used in computing research and especially in [[supercomputing]].<ref name="Voros2009">N. Voros, R. Nikolaos, A. Rosti, M. Hübner (editors): Dynamic System Reconfiguration in Heterogeneous Platforms - The MORPHEUS Approach; Springer Verlag, 2009</ref>

A 2008 paper reported speed-up factors of more than 4 orders of magnitude and energy saving factors by up to almost 4 orders of magnitude.<ref name="Tarek2008">{{cite journal |title= The promise of high-performance reconfigurable computing |authors= Tarek El-Ghazawi |journal= IEEE Computer |volume= 41 |number=2 |pages= 69–76 |date= February 2008 |doi= 10.1109/MC.2008.65 |display-authors=etal|citeseerx= 10.1.1.208.4031 }}</ref>

Some supercomputer firms offer heterogeneous processing blocks including FPGAs as accelerators.{{citation needed |date= August 2011}}

One research area is the twin-paradigm programming tool flow productivity obtained for such heterogeneous systems.<ref name="Esam2009">{{cite journal |author1= Esam El-Araby |author2= Ivan Gonzalez |author3= Tarek El-Ghazawi |title= Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing |journal= ACM Transactions on Reconfigurable Technology and Systems |volume= 1 |number= 4 |date= January 2009 |doi= 10.1145/1462586.1462590 |pages=1–23}}</ref>

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=== Intel ===

[[Intel]]<ref name="intel_altera">{{cite web |url=https://newsroom.intel.com/news-releases/intel-completes-acquisition-of-altera/ |title=Intel completes acquisition of Altera |access-date=15 November 2016}}</ref> supports partial reconfiguration of their FPGA devices on 28&nbsp;nm devices such as Stratix V,<ref name="stratixv_pr">{{cite web |url=https://www.altera.com/products/fpga/features/stxv-part-reconfig.html |title=Stratix V FPGAs: Ultimate Flexibility Through Partial and Dynamic Reconfiguration |access-date=15 November 2016}}</ref> and on the 20&nbsp;nm Arria 10 devices.<ref name="arria10_pr">{{cite web |url=https://www.altera.com/products/design-software/fpga-design/quartus-prime/features.html |title=Intel Quartus Prime Software Productivity Tools and Features |access-date=15 November 2016}}</ref> The Intel FPGA partial reconfiguration flow for Arria 10 is based on the hierarchical design methodology in the Quartus Prime Pro software where users create physical partitions of the FPGA that can be reconfigured<ref name="arria10_pr_docs">{{cite web |url=https://www.altera.com/en_US/pdfs/literature/hb/qts/qts-qps-5v1.pdf |title=Quartus Prime Standard Edition Handbook Volume 1: Design and Synthesis |publisher=Intel |format=PDF |access-date=15 November 2016 |page=4-14–1}}</ref> at runtime while the remainder of the design continues to operate. The Quartus Prime Pro software also support hierarchical partial reconfiguration and simulation of partial reconfiguration.

== Comparison of systems ==

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== Challenges for operating systems ==

One of the key challenges for reconfigurable computing is to enable higher design productivity and a more easy way to use reconfigurable computing systems for users that are unfamiliar with the underlying concepts. One way of doing this is to provide standardization and abstraction, usually supported and enforced by an operating system.<ref name=":0">{{Cite journal|last=Eckert|first=Marcel|last2=Meyer|first2=Dominik|last3=Haase|first3=Jan|last4=Klauer|first4=Bernd|date=2016-11-30|title=Operating System Concepts for Reconfigurable Computing: Review and Survey|url=https://dx.doi.org/10.1155/2016/2478907|journal=International Journal of Reconfigurable Computing|language=en|volume=2016|pages=1–11|doi=10.1155/2016/2478907|issn=1687-7195}} [[File:CC-BY icon.svg|50px]] This article contains quotations from this source, which is available under the [https://creativecommons.org/licenses/by/4.0/ Creative Commons Attribution 4.0 International (CC BY 4.0)] license.</ref>

One of the major tasks of an operating system is to hide the hardware and present programs (and their programmers) with nice, clean, elegant, and consistent abstractions to work with instead. In other words, the two main tasks of an operating system are abstraction and resource management.<ref name=":0" />