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A '''Programmable Interrupt Controller''' ('''PIC''') is a device which allows priority levels to be assigned to its interrupt outputs. When the device has multiple interrupt outputs to assert, it will assert them in the order of their relative priority. Common modes of a PIC include hard priorities, rotating priorities, and cascading priorities. PICs often allow the cascading of their outputs to inputs between each other.
== Common features ==Question : You are in a boat in the middle of a river. You have 2
cigarettes and have to light any one cigarette. You don't have
anything else with you in the boat? How will you do it?
Answers:
a) Take one cigarette and throw it in the w ater. So the boat
will become LIGHTER..... ...using this LIGHTER you can light the other
cigarette.
Another deadly answer, scroll down a little...
OR
b) Another solution: You throw a cigarette up and catch it. Catches win
Matches. Using th e matches that you win, you can light the cigarette.
If that was not enough, one more deadly answer.... scroll down
OR
c) Take water in your hand and drop it drop by drop...(TIP - TIP)
"TIP TIP barsa Pani.
Pani ne aag lagayee."
us aag se hamne cigarette jalayee".
Want more!!....
OR
d) Start praising one cigarette, The other will get jealous & "jalney lage
PICs typically have a common set of registers: Interrupt Request Register (IRR), In-Service Register (ISR), Interrupt Mask Register (IMR). The IRR specifies which interrupts are pending acknowledgement, and is typically a symbolic register which can not be directly accessed. The ISR register specifies which interrupts have been acknowledged, but are still waiting for an End Of Interrupt (EOI). The IMR specifies which interrupts are to be ignored and not acknowledged. A simple register schema such as this allows up to two distinct interrupt requests to be outstanding at one time, one waiting for acknowledgement, and one waiting for EOI.
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