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{{Use American English|date=January 2019}}
{{Unreferenced|date=January 2019}}
'''Random test generators''' (often abbreviated RTG or ISG<ref name=":0">{{Citation |title=Introduction to FORCE-RISCV |date=2023-02-21 |url=https://github.com/openhwgroup/force-riscv |publisher=OpenHW Group |access-date=2023-02-25}}</ref> for Instruction Stream Generator or Instruction Sequence Generator<ref name=":0" />) are a type of [[computer software]] that is used in [[functional verification]] of [[microprocessor]]s. Their primary use lies in providing input stimulus to a [[device under test]].
In a [[Logic simulation|simulation]]/[[Test bench|testbench]] verification environment, the simulator processes input created by the RTG and coverage monitors may be used to verify that the generator is properly testing the design.<ref>{{Cite web |title=Random Test Generator - Bridging the gap {{!}} BCS |url=https://www.bcs.org/membership-and-registrations/member-communities/software-testing-specialist-group/the-tester/newsletter-archive/random-test-generator-bridging-the-gap/ |access-date=2023-02-25 |website=www.bcs.org}}</ref>
Random test generators range in scope from simple [[Scripting language|scripts]] and parameterized [[Macro (computer science)|macro]]s that can be created in a matter of weeks to full featured systems requiring extensive software development. Random test generators are most often created by the designing organizations.
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