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PRAM algorithms cannot be parallelized with the combination of [[Central processing unit|CPU]] and [[dynamic random-access memory]] (DRAM) because DRAM does not allow concurrent access; but they can be implemented in hardware or read/write to the internal [[static random-access memory]] (SRAM) blocks of a [[field-programmable gate array]] (FPGA), it can be done using a CRCW algorithm.
However, the test for practical relevance of PRAM (or RAM) algorithms depends on whether their cost model provides an effective abstraction of some computer; the structure of that computer can be quite different than the abstract model. The knowledge of the layers of software and hardware that need to be inserted is beyond the scope of this article. But, articles such as {{harvtxt|Vishkin|2011}} demonstrate how a PRAM-like abstraction can be supported by the [[explicit multi-threading]] (XMT) paradigm and articles such as {{harvtxt|Caragea|Vishkin|2011}} demonstrate that a PRAM algorithm for the [[maximum flow problem]] can provide strong speedups relative to the fastest serial program for the same problem. The article {{harvtxt|Ghanim|Vishkin|Barua|2018}} demonstrated that PRAM algorithms as-is can achieve competitive performance even without any additional effort to cast them as mutli-threaded programs on XMT.
==Example code==
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