Depletion-load NMOS logic: Difference between revisions

Revision as of 02:47, 30 September 2019

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==History and background==

{{See also|NMOS logic#History}}

Following the invention of the [[MOSFET]] by [[Mohamed Atalla]] and [[Dawon Kahng]] at [[Bell Labs]] in 1959, they demonstrated MOSFET technology in 1960.<ref name="computerhistory">{{cite journal|url=https://www.computerhistory.org/siliconengine/metal-oxide-semiconductor-mos-transistor-demonstrated/|title=1960 - Metal Oxide Semiconductor (MOS) Transistor Demonstrated|journal=The Silicon Engine|publisher=[[Computer History Museum]]}}</ref> They [[Semiconductor device fabrication|fabricated]] both pMOS and nMOS devices with a [[10 µm process|20{{nbsp}}µm process]]. However, the nMOS devices were impractical, and only the pMOS type were practical working devices.<ref name="Lojek">{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=[[Springer Science & Business Media]] |isbn=9783540342588 |pages=321-3}}</ref>

A more practical NMOS process was developed several years later by Dale L. Critchlow and [[Robert H. Dennard]] at [[IBM]] in the 1960s. The first IBM NMOS product was a [[memory chip]] with 1{{nbsp}}[[kibibit|kb]] data and 50{{ndash}}100 [[nanosecond|ns]] [[access time]], introducedwhich in 1966 and enteringentered large-scale manufacturing soonin afterthe early 1970s. This led to MOS [[semiconductor memory]] replacing earlier [[bipolar junction transistor|bipolar]] memory and [[ferrite-core memory]] technologies byin the early 1970s.<ref>{{cite journal |last1=Critchlow |first1=D. L. |title=Recollections on MOSFET Scaling |journal=IEEE Solid-State Circuits Society Newsletter |date=2007 |volume=12 |issue=1 |pages=19–22 |doi=10.1109/N-SSC.2007.4785536 |url=https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4785536}}</ref>

===Silicon gate===