Address decoder: Difference between revisions

Revision as of 19:53, 17 December 2019

Revision as of 23:06, 9 June 2021

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A single address decoder with n address input bits can serve up to 2ⁿ devices. Several members of the [[List of 7400 series integrated circuits|7400 series]] of [[integrated circuit]]s can be used as address decoders. For example, when used as an address decoder, the 74154<ref>[httphttps://webassets.mitnexperia.educom/6.115/wwwdocuments/datasheetsdata-sheet/74hc15474HC_HCT154.pdf Datasheet for 74HC15474HCT154]</ref> provides four address inputs and sixteen (i.e., 2⁴) device selector outputs. An address decoder is a particular use of a [[binary decoder]] circuit known as a "[[demultiplexer]]" or "demux" (the 74154 is commonly called a "4-to-16 demultiplexer"), which has many other uses besides address decoding.

Address decoders are fundamental building blocks for systems that use [[Bus (computing)|buses]]. They are represented in all integrated circuit families and processes and in all standard [[FPGA]] and [[Application-specific integrated circuit|ASIC]] libraries. They are discussed in introductory textbooks in digital logic design.<ref name="TAoE"/>