Classic RISC pipeline: Difference between revisions

Revision as of 03:59, 11 January 2020

Revision as of 17:16, 4 February 2020

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===Instruction decode===

Unlike earlier microcoded machines, the first RISC machinesRISCmachines had no [[microcode]]. Once fetched from the instruction cache, the instruction bits were shifted down the pipeline, so that simple combinational logic in each pipeline stage could produce the control signals for the datapath directly from the instruction bits. As a result, very little decoding is done in the stage traditionally called the decode stage. A consequence of this lack of decoding meant however that more instruction bits had to be used specifying what the instruction should do (and also, what it should not), and that leaves fewer bits for things like register indices.

All MIPS, SPARC, and DLX instructions have at most two register inputs. During the decode stage, these two register names are identified within the instruction, and the two registers named are read from the [[register file]]. In the MIPS design, the register file had 32 entries.