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→Solution A. Bypassing: The AND instruction does bitwise-and (C &) not logical-and (C &&) |
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<source lang="nasm">
SUB r3,r4 -> r10 ; Writes r3 - r4 to r10
AND r10,r3 -> r11 ; Writes r10
</source>
The instruction fetch and decode stages send the second instruction one cycle after the first. They flow down the pipeline as shown in this diagram:
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